The present invention relates to a semiconductor integrated circuit device and a manufacturing method of the same. More particularly, the present invention relates to a technique effectively applicable to a semiconductor integrated circuit device, in which a DRAM (Dynamic Random Access Memory) and a logic circuit are mounted together, and a manufacturing method of the same.
The DRAM has a MISFET (Metal Insulator Semiconductor Field Effect Transistor) for data transfer and a capacitor for data storage connected in series to this MISFET. This capacitor for data storage is formed by, for example, sequentially depositing silicon to be a lower electrode, tantalum oxide to be a capacitor insulating film, and a refractory metal film to be an upper electrode.
Also, in this capacitor for data storage, the scaling down of the device and the increase of the capacitance thereof are achieved by forming a deep hole through the insulating film and then forming a lower electrode and a capacitor insulating film on the side wall and the bottom surface of the hole.
For further increase of the capacitance, a technique is employed in which projections made of silicon grains are provided on a surface of the silicon to be a lower electrode to create surface irregularities, and thereby increasing the surface area. The projections made of silicon grains are called HSG (Hemispherical Grained) silicon or rugged silicon.
A technique capable of effectively forming the HSG polysilicon is disclosed in, for example, Japanese Patent Application Laid-Open Publication No. 2000-22110. This technique is briefly described as follows: Moisture contained in an interlayer insulating film is desorbed and the desorbed moisture reacts to the polysilicon film below the interlayer insulating film during the high temperature heat treatment for forming the HSG polysilicon film. As a result, an SiO2 film is formed on the surface of the polysilicon film. For its prevention, a heat treatment at a temperature higher than the temperature at which the moisture is desorbed is performed immediately before the above-described high temperature heat treatment.
Inventors of the present invention have been engaged in research and development of the DRAM and the like, and have been attempting to increase the capacitance by means of the introduction of the rugged polysilicon.
However, since the growth of the rugged polysilicon is hindered due to the effect of the moisture in the insulating film on which the rugged polysilicon is formed, it is difficult to obtain the sufficient surface area of the rugged polysilicon. Thus, such a method is under consideration that a high temperature heat treatment is performed to remove the moisture in the insulating film, and then, to have the rugged polysilicon grown. In this case, however, the properties of the MISFET in the under layer are deteriorated due to the high temperature heat treatment.
Especially, in the so-called system LSI (Large Scale Integrated Circuit) in which the DRAM and the logic LSI are formed on the same semiconductor substrate, the logic circuit is formed by appropriately combining an n channel MISFET and a p channel MISFET, and the properties of these MISFETs are deteriorated due to the high temperature heat treatment.
For example, in these MISFETs, a so-called dual gate structure is employed, in other words, an n type gate electrode is used as the gate electrode of the n type MISFET and a p type gate electrode is used as the gate electrode of the p type MISFET. This is because if an n type gate electrode is used as the gate electrode of the p type MISFET, the channel thereof is formed at the position apart from the substrate surface (embedded channel), and the control of the potential applied to the gate electrode becomes difficult.
However, boron (B) implanted to make the p type gate electrode is prone to diffuse (leak) by the heat treatment. If the boron is diffused into the semiconductor substrate through a gate insulating film, the concentration profile of the semiconductor substrate is changed, resulting in the deterioration of its properties (e.g., variation of the threshold voltage).
In addition to the concentration profile of the semiconductor substrate, the heat treatment causes an adverse effect on various properties of the MISFET such as the concentration profile of the source and drain regions of the MISFET.
It is an object of the present invention to reduce the load due to the heat treatment to a semiconductor integrated circuit device having a DRAM memory cell.
It is another object of the present invention to improve the properties of a DRAM memory cell.
It is another object of the present invention to improve the properties of a semiconductor integrated circuit device having a DRAM and a logic circuit constituted of an n channel MISFET and a p channel MISFET.
The above and other objects and novel characteristic of the present invention will be apparent from the descriptions and the accompanying drawings of this specification.
The typical ones of the inventions disclosed in this application will be briefly described as follows.
1. In an aspect of the manufacturing method of a semiconductor integrated circuit device according to the present invention, an insulating film is formed above a MISFET of a memory cell, which is formed of the MISFET and a capacitor formed on a main surface of a semiconductor substrate, by the plasma CVD method at a temperature of 450xc2x0 C. to 700xc2x0 C.; a trench is formed by etching the insulating film; and a silicon film is deposited on the insulating film and in the trench, and then, the silicon film on the insulating film is removed to form a lower electrode of the capacitor on the inner wall of the trench.
2. In another aspect of the manufacturing method of a semiconductor integrated circuit device according to the present invention, a first insulating film is deposited above a MISFET of a memory cell, which is formed of the MISFET and a capacitor formed on a main surface of a semiconductor substrate, at a predetermined temperature; a second insulating film is deposited on the first insulating film at a temperature higher than the predetermined temperature; a trench is formed by etching the first and second insulating films; and a silicon film is deposited on the second insulating film and in the trench, and then, the silicon film on the second insulating film is removed to form a lower electrode of the capacitor on the inner wall of the trench.
3. In another aspect of the manufacturing method of a semiconductor integrated circuit device according to the present invention, a MISFET is formed on a main surface of a semiconductor substrate; and then, an insulating film containing an impurity is formed above the MISFET by the plasma CVD method at a temperature of 450xc2x0 C. to 700xc2x0 C.
4. In another aspect of the manufacturing method of a semiconductor integrated circuit device according to the present invention, a MISFET is formed on a main surface of a semiconductor substrate; a first insulating film is deposited on the MISFET at a predetermined temperature and the surface of the first insulating film is planarized; and then a second insulating film containing an impurity is formed on the first insulating film at a temperature higher than the predetermined temperature.
5. In an aspect of the semiconductor integrated circuit device according to the present invention, the semiconductor integrated circuit device is provided with a MISFET formed on a main surface of a semiconductor substrate; and a capacitor connected in series to the MISFET,
wherein the capacitor is provided with a lower electrode made of a silicon film, which is formed at a concave portion in a lamination layer of a first insulating film formed above the MISFET and a second insulating film formed on the first insulating film and having smaller impurity content than the first insulating film; a capacitor insulating film formed on the lower electrode; and an upper electrode formed of a conductive film formed on the capacitor insulating film.
6. In another aspect of the semiconductor integrated circuit device according to the present invention, the semiconductor integrated circuit device is provided with a MISFET formed on a main surface of a semiconductor substrate; and a capacitor connected in series to the MISFET,
wherein the capacitor is provided with a lower electrode made of a silicon film, which is formed at a concave portion in a lamination layer of a first insulating film formed above the MISFET and a second insulating film which is thinner than the first insulating film and formed on the first insulating film; a capacitor insulating film formed on the lower electrode; and an upper electrode formed of a conductive film formed on the capacitor insulating film.